ADDRESS WIDTH from RAM DEPTH

The $clog2 system task was added to the SystemVerilog extension to Verilog (IEEE Std 1800-2005). This returns an integer which has the value of the ceiling of the log base 2. The DEPTH need not be a power of 2.

module tb;

parameter DEPTH = 5;
parameter WIDTH = $clog2(DEPTH);

initial begin
    $display("d=%0d, w=%0d", DEPTH, WIDTH);
    #5 $finish;
end

endmodule

Running a simulation will display this:

d=5, w=3

However, I do not know of a synthesis tool which supports $clog2. If you need to synthesize your code, you can use a function. This was copied from the IEEE 1364-2001 Std, but there are other versions floating around the web:

function integer clogb2;
    input [31:0] value;
    begin
        value = value - 1;
        for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
            value = value >> 1;
        end
    end
endfunction

My experience has been that using the function is more trouble than it's worth for synthesizable code. It has caused problems for other tools in the design flow (linters, equivalence checkers, etc.).

While $clog2 is the correct answer, until the tool vendors catch up, you can implement your own clog2 function as a verilog-2001 macro, which will work with all synthesis and simulation tools.

Such as:

`define CLOG2(x) \
   (x <= 2) ? 1 : \
   (x <= 4) ? 2 : \
   (x <= 8) ? 3 : \
   (x <= 16) ? 4 : \
   (x <= 32) ? 5 : \
   (x <= 64) ? 6 : \
   ..etc, as far as you need to go..
   (x <= 4294967296) ? 32 : \
   -1

parameter FOO_MAX_VALUE = 42;
parameter FOO_WIDTH = `CLOG2(FOO_MAX_VALUE);

Where the final "-1" is used to produce an illegal value the the simulator should flag.

(late edit: oops, fixed my off-by-one error!)