Bypass capacitors needed in low-frequency digital logic systems?

The relevant factor is the rise/fall times, not the clock rate. Here are two relevant papers. Conventionally, designers stick to 100nF cap per IC. Bear in mind that they serve multiple purposes: signal integrity, power supply noise, internal IC operation, radiated EMI, susceptability to EMI. Using an SMT 0805 or smaller (smaller is better) shouldn't take too much board space.

When it comes to decoupling, clock frequency is rarely what determines how to do it. The primary determination on simple chips (like quad-gates, buffers, etc.) is the edge rate (or slew rate) of the output signals. The faster that signal transitions from 0 to 1 and 1 to 0 is the edge rate. The faster the edge rate the more decoupling caps are required.

Edge rate is still very important for complex chips, but the logic inside the chip becomes a significant factor too. Essentially, there are signals inside the chip that are transitioning too, and although you can't see or probe them they are important.

Decoupling caps are important, don't skimp on them-- especially when your power distribution wiring has more impedance than you'd like, as in a breadboard.