Can microcontrollers be run at arbitrarily low clock frequencies?

Yes. If the datasheet says "fully static operation", then you can clock it at any speed, even 0 Hz. A "dynamic" chip needs to have a clock at a specific rate or it loses its state.

I am posting another answer, just because the last question you had was not answered before.

Todbot is completely correct. It will also draw lower power at lower speeds. It also means if you supply it's clock from another processor, for example, you could stop supplying it at any point and then start clocking it later, as long as you do not go faster than max speed, you will be fine.

The Chips I have get an order of magnitude change between 32768Hz oscillator and a 1MHz one. I have had applications where I did not need speed, I just needed another little guy doing some basic data handling for me.

Hope this helps.

Most modern microcontroller designs will work with any pattern on their clock input, provided only that no high pulse is below a certain minimum length, no low pulse is below a certain minimum length, and no low-high-low or high-low-high pulse pair is below a certain length. Essentially what happens is that after the chip does all of the actions associated with a particular clock edge, the chip will be in a state where it is doing nothing but waiting for the next clock edge. If the next clock edge doesn't arrive for ten days then (unless the chip has some external watchdog) the chip will be in the same state as if the edge had arrived the moment the chip was ready for it.

Note that in general, pausing the clock on a microcontroller will reduce current consumption substantially, but not as much as using the "sleep" feature. Most microcontrollers' current consumption in "run" mode can be pretty well estimated as a constant quiescent current plus a certain amount of current per cycle per second (which might be more 'naturally' expressed as charge per cycle). For example, a chip might have a quiescent current of 10uA, plus a current of 0.1mA/MHz (100pC/cycle). Running such a chip at 10MHz would yield a current of 1.01mA. Running it at 1MHz would yield 0.11mA. Running it at 100KHz would yield 0.02mA. Running it at 1Hz woudl yield 0.0100001mA. On the other hand, the chip might offer a sleep current of 1uA. Generally, entering sleep mode will completely power off areas of the chip that aren't going to do anything useful while the chip is sleeping, thereby avoiding any leakage current such areas might have. It will in some cases also reduce the voltage to areas like register files to a level where the register files can hold their contents, but not access them very quickly (since they won't be accessed at all, access speed doesn't matter).

Some older microprocessors, microcontrollers, and other devices had maximum clock-high and/or clock-low times. Such processors made use of dynamic logic to save circuitry. As an example of dynamic logic, consider a shift register: a typical static register bit requires a two-transistor circuit to hold the value, while a dynamic register bit holds the value on the gate of a readout transistor. A two-phase-clocked dynamic shift register may be realized in NMOS using four NFETs and two resistors per bit. A static shift register would require eight NFETs and four resistors per bit. Dynamic logic approaches are not nearly so common today. Back in the 1970's, gate capacitance was substantial and there wasn't any getting rid of it. There was thus no particular reason not to take advantage of it. Today, gate capacitance is generally much lower, and chip makers are actively trying to reduce it further. Making dynamic logic work reliably would often require deliberately working to increase gate capacitance. In most cases, the extra chip area needed to increase capacitance could be just as effectively used to add more transistors so as to make the capacitance unnecessary.