Can we reduce power consumption of digital interfaces by using high impedance transmission lines?

While, in theory, high impedances would reduce power dissipation for the same voltage swing, there are several important issues in practice.

1) It's the power, not the voltage, of a signal that determines signal to noise ratio. If you must swing the full rail, then you'd win by increasing the impedance. However if you launch a specific power, then low impedance is not so much of a problem, just reduce your swing.

2) It's not physically practical to get impedances of much more than 100 ohms on a board. The signal conductor needs to get unmanufacturably thin, the space to the ground plane space-consumingly large. The impedance goes as the log ratio of spacing to centre, so you rapidly run out of improvement.

There are other reasons we like a fairly meaty centre conductor, as well as the fab being able to make it. The copper losses vary inversely with the conductor surface area (all the RF flows in the surface), and in fact 75 ohms is the lowest loss geometry (which it why it's used for receive antenna feeds). The highest power handling geometry is around 35 ohms, dependant on heating and surface electric fields. These two figures are why 50 ohms was chosen as a compromise between the two competing criteria as the 'standard' impedance for test gear.

3) In a high speed detector, input impedance is a critical parameter. It's easier to handle with a lower impedance line, for much the same geometrical reasons that you can't make a high Z line on a board, you can't really make a high Z line receiver IC.

This termination resistance closes the current loop between two differential signal lines and creates a decent amount of power loss so that low voltage amplitudes are required to reduce power consumption.

I think there's a misconception here about how transmission lines work. The purpose of receiver-end termination is to dissipate all the power, in order to avoid it being reflected.

Think of it this way: there is a "pulse" travelling down the line. This pulse embodies a certain amount of energy. Along the way, some of that energy is dissipated by the non-idealness of the transmission line. At the receiver end, the pulse has to have a sufficient amplitude in order to be distinguished from noise. Working backwards from that gives you the amount of energy that has to be put into the pulse "launch" in order to ensure it arrives cleanly.

If the receiver is not impedance-matched, some of the signal will reflect, which worsens your signal-detection problems.

If this sounds like the requirements for radio SNR, there's a very good reason: a transmission line is very similar to a radio wave that's (mostly) contained in a wire rather than a waveguide or allowed to radiate into free space.

The solutions for reducing energy requirement are similar:

• improve SNR: improve the shielding of the transmission line and reduce its coupling to noise sources
• improve signal discrimination: better channel coding schemes, more sensitive receivers
• reduce path loss: improve the shielding of the transmission line and reduce its coupling to external losses
• reduce ohmic resistance of the transmission line
• reduce margin: rather than choosing a power level that's guaranteed to work under adverse circumstances, "train" the transmitter to the minimum reliable power level. Currently the most widely used wired interface with any kind of training is for DRAM, but it's more common in wireless interfaces.

Well you could reduce power, at least in the interfaces, but this brings up a whole host of other issues.

On a printed wiring board, higher impedances mean narrower line widths and larger spacing between the layers. Narrower line widths negatively impact manufacturing yield, and larger spacings between layers mean more material and thicker boards. Both of these drive up PWB cost. Even with these heroics it's tough to get the single-ended impedance much above 60 or 70 ohms, assuming ~5.6 mils between layers, which is typical for our designs - 0.134" total board thickness and 24 layers.

Then there's the issue that most high speed test equipment is designed around 50 ohm characteristic impedances, which would complicate making measurements on interfaces with other than 50 ohm impedance.