Cascaded logic inverters

TL:DR

It's for obtaining the right driving strength, the right input capacitance and the lowest latency.

Explanation

Logically there is no difference between one or three inverters, but...

This kind of buffer is made to drive a higher load than just a single inverter, and this has to do with speed. The problem is that a CMOS gate can drive a current proportional to the width of its channel: doubling the channel width, you'll be able to charge a given capacitor twice as fast.

So, why not just use very wide transistors to have the highest current?

Because, if you double the channel width, you also double the input capacitance of the gate, so the stage before will take twice the time to drive the gate. So you need a gate which has the minimum possible input capacitance, while having as much as driving strength as possible.

This is obtained by cascading several inverters (the most elementary CMOS gate) with increasing channel width, so that the first has the required input capacitance and the last has the required driving strength.

The tradeoff now is that each inverter has also a fixed amount of latency, so you can't solve it just cascading many many inverters. There are specific formulas, also described in Rabaey-Chandrakasan-Nikolic book about integrated circuits design (expensive but very good!).

That is called a super buffer. It provides a high current capability at the output, keeps a low input capacitance, and tries to minimize the total delay, by progressively sizing the inverters (larger towards the output).

References: A, B, C, D.