How can I specify "don't care" signals in VHDL?

I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supposed to - the logic generated is reduced as expected when the output is defaulted to '-' ('X' works too, by the way). More on the approaches you listed:

• Not assigning the signal isn't really an option for your example, of course, if you don't want latches. If it's a clocked process, you're slightly better off, but you'll still get enables where you might not need them. Maybe I'm missing your intent here.

• '-', as previously noted, is probably the best option, for both semantic and practical reasons.

• Depends on what you mean by "undefined". 'X' is technically "unknown". 'U' is for uninitialized signals, which ModelSim displays as "X" for hex representations. 'X' does seem to work, though, as I noted above.

Another alternative would be to do the optimization yourself and remove one case from being tested explicitly:

if instruction(15 downto 8) = "11111001" then
  write_data <= std_ulogic_vector(resize(signed(instruction(7 downto 4)), 16));
else
  write_data <= std_ulogic_vector(resize(signed(instruction(7 downto 0)), 16));
end if;

This has significant disadvantages (mostly related to code clarity), though, and I would probably opt for a more ideal solution.

Incidentally, '-' is also commonly used with std_match(), which I would consider using for your decoding, e.g.:

if std_match(instruction(15 downto 8), "1100----") then

Though at that point, you're probably better off just using case?.

In short: It's legal VHDL and it's typically supported by synthesis tools.

It is however rather uncommon to see it used. I don't really know why. Your code seems to me to be a good example of when it would be meaningful to use it.

There is however one drawback that one should be aware of: at synthesis, the functions driving outputs where don't care's are involved could be different between synthesis runs. This makes the synthesis less deterministic. If outputs that have been defined as don't care are used (by mistake), this can make the error harder to find.

Tool support

At least the following tools will accept don't cares and make use of the optimization possibilities:

• Xilinx (ref.: "XST User Guide")
• Altera (ref.: "Recommended HDL Coding Styles")
• Synplify (ref.: "Synplify reference manual")

Xilinx and Altera will treat '-' and 'X' as don't care, Synplify will treat those and furthermore 'U' and 'W' (weak) as don't care.