How is a VHDL variable synthesized by synthesis tools

I would distinguish three possibilities:

1. A VHDL variable has no hardware representation at all. Assume the following example

   signal a,b,c : integer;  
   ...  
   process ( clk ) is  
   variable var : integer := 0;  
   begin  
   if ( rising_edge(clk) ) then  
   var := a + b;  
   c <= var;  
   end if;  
   end process;
   

   The variable var is not really synthesized as combinatorial logic at all (assuming this is what was meant in the question). It's rather the right hand side of the assignment a + b that is synthesized into hardware. Strictly speaking a variable never is synthesized into combinatorial logic.

2. A variable merely holds an intermediate result, which is either evaluated in the same clock cycle -> no hardware synthesized ( this is 1) again ), or is evaluated in the following clock cycle -> a flipflop is synthezised.

3. One of those dreaded latches is inferred in such cases where conditional branches exist in which the variable is assigned neither a new value (depending on some signals) nor a default value. Usually this case happens unintended :-)

If you use the value in a variable before you store it, you get the value that was stored last time the process stored it (in a clocked process, the value from a previous clock cycle). That is synthesised as a register or FF.

Of course, in the first clock cycle you get garbage, unless you initialised the variable in a reset clause.