How much does it cost to have a custom ASIC made?

I looked into ASIC's a while ago and here's what I found:

Everybody has different definitions for the word "ASIC". There are (very roughly) three categories: FPGA Conversions, "normal" ASIC, and "full custom". As expected, these are in order of increasing price and increasing performance.

Before describing what these are, let me tell you how a chip is made... A chip has anywhere from 4 to 12+ "layers". The bottom 3 or 4 layers contains the transistors and some basic interconnectivity. The upper layers are almost entirely used to connect things together. "Masks" are kind-of like the transparencies used in the photo-etching of a PCB, but there is one mask per IC layer.

When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (8 layers, 35 to 50 nm) to run US$1 Million! So it is no great surprise to know that most of the "cheaper" ASIC suppliers try very hard to keep the costs of the masks down.

FPGA Conversions: There are companies that specialize in FPGA to ASIC conversions. What they do is have a somewhat standard or fixed "base" which is then customized. Essentially the first 4 or 5 layers of their chip is the same for all of their customers. It contains some logic that is similar to common FPGA's. Your "customized" version will have some additional layers on top of it for routing. Essentially you're using their logic, but connecting it up in a way that works for you. Performance of these chips is maybe 30% faster than the FPGA you started with. Back in "the day", this would also be called a "sea of gates" or "gate array" chip.

Pros: Low NRE (US$35k is about the lowest). Low minimum quantities (10k units/year).

Cons: High per-chip costs-- maybe 50% the cost of an FPGA. Low performance, relative to the other solutions.

"Normal" ASIC: In this solution, you are designing things down to the gate level. You take your VHDL/Verilog and compile it. The design for the individual gates are taken from a library of gates & devices that has been approved by the chip manufacturer (so they know it works with their process). You pay for all the masks, etc.

Pros: This is what most of the chips in the world are. Performance can be very good. Per-chip costs is low.

Cons: NRE for this starts at US$0.5 million and quickly goes up from there. Design verification is super important, since a simple screw-up will cost a lot of money. NRE+Minimum order qty is usually around US$1 million.

Full Custom: This is similar to a Normal ASIC, except that you have the flexibility to design down to the transistor level (or below). If you need to do analog design, super low power, super high performance, or anything that can't be done in a Normal ASIC, then this is the thing for you.

Pros: This requires a very specialized set of talents to do properly. Performance is great.

Cons: Same con's as Normal ASIC, only more so. Odds of screwing something up is much higher.

How you go about this really depends on how much of the work you want to take on. It could be as "simple" as giving the design files to a company like TSMC or UMC and they give you back the bare wafers. Then you have to test them, cut them apart, package them, probably re-test, and finally label them. Of course there are other companies that will do most of that work for you, so all you get back are the tested chips ready to be put on a PCB.

If you have gotten to this point and it still seems like an ASIC is what you want to do then the next step would be to start Googling for companies and talking with them. All of those companies are slightly different, so it makes sense to talk with as many of them as you can put up with. They should also be able to tell you what the next step is beyond talking with them.

There are two major ways to get an ASIC made if you're looking at third party processes, such as IBM, ONsemi, STMicro, etc. The first is to work directly with the foundry (manufacturer), and the second is to work with a group that processes smaller orders.

Working directly with the manufacturer, you are typically buying a production run for a particular chip. This will give you multiple wafers with multiple copies of a reticule. A reticule will typically be around 15 to 20mm². You would be able to put whatever you want in that space, and you would then later divide the wafer into the individual designs. If you were making a production run of a single chip, your design would be tiled here. I don't know the prices for this, but it would probably run something like: \$Cost = Masks + N \times Wafers\$, where the masks are a dominant portion of your cost. I would estimate that for the latest 40nm processes, the costs start around $2 million.

If you are not looking for large volumes, or you are wanting to prototype a design, then there are companies that will buy a run from a foundry for one or two wafers, and then sell out space in the reticule. There are two major companies: MOSIS and CMP. They plan on buying only one or two wafers and a set of masks, so their production costs are basically fixed. Their prices are typically based on the size of your design in mm². MOSIS doesn't publish their rates, but CMP's cheapest rate on a 0.35 micron process for 650 Euros/mm². A non-trivial design will probably cost $3000 or more for 40 chips. The finer the feature size, the more expensive it is to make the masks.

Another item to consider is that the design software needed to design and verify IC's is NOT cheap, unless you're doing it from a university setting.

Although it's true that creating a chip is very expensive, TSMC and other fabs do provide "shuttle services" that put many devices from many people on the die and reduce the price significantly. I've even hear a company getting a few samples of it's devices for $1500, which is extremely low when you consider the alternatives. Before anything, it's best to implement as much as possible on an FPGA to ensure the logic is correct, etc etc.

Take a look here: http://www.tsmc.com/english/dedicatedFoundry/services/cyberShuttle.htm