How to assign value to bidirectional port in verilog?
If you must use any port as inout, Here are few things to remember:
- You can't read and write inout port simultaneously, hence kept highZ for reading.
- inout port can NEVER be of type reg.
- There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).
For e.g. I'll write your code in following way.
module test (value, var);
inout value;
output reg var;
assign value = (condition) ? <some value / expression> : 'bz;
always @(<event>)
var = value;
endmodule
BTW When var is of type wire, you can read it in following fashion:
assign var = (different condition than writing) ? value : [something else];
Hence as you can see there is no restriction how to read it but inout port MUST be written the way shown above.
I hope that explains it to you.