How to double my clock's frequency using digital design

I am trying to double my clock's frequency using only gates, flip flops or whatever

Start with a 20 MHz clock (that comes under the "whatever" umbrella) and reduce it to 10 MHz where it is needed using a flip-flop clock divider.

A PLL is generally required to achieve what you want to do. Trying to use just logic to do this requires the addition of some extra delays via R/C time constants to bring the 2x pulses up to near 50% duty cycle. However that will not generally happen inside an FPGA without bringing some signals to pins on the part where the R/C can be connected and then fed back into other pins. Another limitation is that such scheme will not be right on 50% duty cycle and for a given set of R/C values will only be useful at a particular narrow range of input frequency.

Doubling the frequency can be as simple as this:

thanks to the gate propagation delay (I actually used this to overclock a TRS-80 when I was young).

Solving the duty cycle problem could be done (approximately) by changing the number of gates in series, but would only work for one frequency (and would probably be sensitive to components charateristics, temperature, etc.)

You could double the frequency twice and divide it once with a flip-flop to obtain a perfectly square signal, like Andy said.