How to prevent "Def Con" and simulation running at femtoseconds / second (running forever) for 1,600-run simulation

Try this: for all sources add Rser=0.1, and for the 3V one add Cpar=1m, and for both capacitors add Rser=10m. If (unwanted) very high frequency oscillations start to appear because of the inductor, try adding Rpar=100k to the inductor, or even lower. Don't shy away from setting parasitics, they helo with convergence. If need arises, also don't be afraid to add small capacitances from key nodes to ground -- they help smooth out those discontinuities caused by very sharp transisions.

One key thing to remember is that voltage sources are not that convergence friendly in LTspice, but when you addRser, internally they are converted to current sources, which are far superior in terms of convergence.

When a simulation descends to machine limit calculation it is a sign that the simulation sees or expects chaotic output.

This can be due to a divergent solution (e..g runaway positive feedback, multiple voltage dependent sources ) without same limits on power or frequency or otherwise .

If you are really testing 1600 transistor models and some exhibit this and some don't it is possible that some are simply not suitable and not appropriately modeled for this application/operating regime and break the sim

Or they are more ideal and some more accurately model secondary parameter or model features that keeps things from diverging.

Usually I take it as a sign do to one of the following

1. Modularize my simulation and create individual parametrized models of major sub parts
2. Alternatively Simplify the Sim and what I am asking of it
3. Triple check my simulation schematic and analysis options
4. Only used verified good and appropriate models compatible with ltspice