Change Makefile variable value inside the target body

Here is the solution I use:

PASSWORD = abc123

main: sub
    @echo "in main" $(PASSWORD)

sub:
    @echo "in sub" $(PASSWORD)
    $(eval PASSWORD=qwerty)
    @echo "in sub" $(PASSWORD)

If you run make main then the output is:

in sub abc123
in sub qwerty
in main qwerty

You can see that the original value "abc123" is overwritten in the sub and the new value "qwerty" is visible at the main level.

Another answer is here: Define make variable at rule execution time.

For the lazy, you can have rules like the following (FLAG and DEBUG are my variables):

.DBG:
    $(eval FLAG += $(DEBUG))

Yes, there is an easy way to do it, and without rerunning Make. Use a target-specific variable value:

test: clean debug_compile

debug_compile: ERLCFLAGS += -DTEST
debug_compile: compile compile_test;