FPGA: count up or count down?

Optimizing to this level will break your heart. The result could change because of the technology of the FPGA you're using, other factors in the FPGA, but also because of factors outside of your control, including the fitter's random number seed.

Having said that, I believe that option 3 will be the best. Options 1 and 2 have a comparator/OR gate going between the counters so that it can signal that the target number has been reached. Option 2 may be slightly faster than 1, since it all can be straight OR'd together without any inverters, but again you run into small technology differences where it may be faster to AND or XOR.

Option 3 skips the comparison for the low cost of one extra bit in the counter. This should be worth it, unless you are severely restricted in flip-flops.

One fun fact about counters is that they tend to be grouped into a device specific size within a logic block, and you will see the timing change more than expected if this extra bit pushes you out of that group.

One other option would be to initialize the counter to 6 (=2⁴ - 10), count up, and then reset when the carry output activates (i.e., the FFs are all ones).

The advantage of this is that it doesn't require an extra FF, and many FGPAs have dedicated auxiliary logic to speed up this kind of carry operation in a counter or adder circuit.

Depends. For example: flip-flop propagation delay for 0→1 and 1→0 can be different, and hence a counter's transition delays for 000→001 and 001→000 can be slightly different. It may be higher or lower, depending on the cmos technology used in FPGA. So you have to synthesize and find out which one has better timing performance.