How to pass target name to list of sub-makefiles?

You could simply use the MAKECMDGOALS variable:

Make will set the special variable MAKECMDGOALS to the list of goals you specified on the command line. If no goals were given on the command line, this variable is empty.

$(SUB_DIRS):
    +$(MAKE) -C $@ $(MAKECMDGOALS)

The + sign is important so the underlying job server also handles the recursive make calls with the right amount of threads/core.

---

You can also use the $(foreach ) function like this:

clean:
    $(foreach DIR, $(SUB_DIRS), $(MAKE) -C $(DIR) $@;)

Do note as @musicmatze mentionned in the comments that Make flags (like -j) won't be passed to the sub-make processes correctly here.

I finally got it work. The approach is:

SUB_DIRS        = $(wildcard */.)
SUB_DIRS_ALL    = $(SUB_DIRS:%=all-%)
SUB_DIRS_TEST   = $(SUB_DIRS:%=test-%)
SUB_DIRS_CLEAN  = $(SUB_DIRS:%=clean-%)

#
# Standard task
#
all: $(SUB_DIRS_ALL)

test_uml: $(SUB_DIRS_TEST)

clean: $(SUB_DIRS_CLEAN)

$(SUB_DIRS_ALL):
        @$(MAKE) $(MAKE_FLAGS) -C $(@:all-%=%)

$(SUB_DIRS_TEST):
        @$(MAKE) $(MAKE_FLAGS) -C $(@:test-%=%) test

$(SUB_DIRS_CLEAN):
        @$(MAKE) $(MAKE_FLAGS) -C $(@:clean-%=%) clean

I found this solution here: http://lackof.org/taggart/hacking/make-example/