making all rules depend on the Makefile itself

This looks like one more simple, useful, logical thing that Make should be able to do, but isn't.

Here is a workaround. If the clean rule is set up correctly, Make can execute it whenever the makefile has been altered, using an empty dummy file as a marker.

-include dummy

dummy: Makefile
    @touch $@
    @$(MAKE) -s clean

This will work for most targets, that is targets that are actual files and that are removed by clean, and any targets that depend on them. Side-effect targets and some PHONY targets will slip through the net.

Since GNU make version 4.3 it is now possible with the use of those two special variable:

1. .EXTRA_PREREQS
   • To add new prerequisite to every target
2. MAKEFILE_LIST
   • To get the path of the make file

To have every target depend on the current make file:

Put near the top of the file (before any include since it would affect the MAKEFILE_LIST) the following line:

.EXTRA_PREREQS:= $(abspath $(lastword $(MAKEFILE_LIST)))

To have every target depend on the current make file and also the make files which were included

Put the following line at the end of your file:

    .EXTRA_PREREQS+=$(foreach mk, ${MAKEFILE_LIST},$(abspath ${mk}))

The only answer I know to this is to add makefile explicitly to the dependencies. For example,

%.o: %.c makefile
        $(CC) $(CFLAGS) -c $<