View size of CPU cache through the command-line?

lscpu will provide the info you're looking for.

lscpu | grep "cache" to filter out only cache info. This will result in something like:

L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              3072K

sysfs

for d in /sys/devices/system/cpu/cpu0/cache/index*;
  do tail -c+1 $d/{level,type,size}
  echo
done

Gives:

==> /sys/devices/system/cpu/cpu0/cache/index0/level <==
1

==> /sys/devices/system/cpu/cpu0/cache/index0/type <==
Data

==> /sys/devices/system/cpu/cpu0/cache/index0/size <==
32K

==> /sys/devices/system/cpu/cpu0/cache/index1/level <==
1

==> /sys/devices/system/cpu/cpu0/cache/index1/type <==
Instruction

==> /sys/devices/system/cpu/cpu0/cache/index1/size <==
32K

==> /sys/devices/system/cpu/cpu0/cache/index2/level <==
2

==> /sys/devices/system/cpu/cpu0/cache/index2/type <==
Unified

==> /sys/devices/system/cpu/cpu0/cache/index2/size <==
256K

==> /sys/devices/system/cpu/cpu0/cache/index3/level <==
3

==> /sys/devices/system/cpu/cpu0/cache/index3/type <==
Unified

==> /sys/devices/system/cpu/cpu0/cache/index3/size <==
8192K

getconf

getconf -a | grep CACHE

gives:

LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  262144
LEVEL2_CACHE_ASSOC                 8
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  20971520
LEVEL3_CACHE_ASSOC                 20
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

Or for a single level:

getconf LEVEL2_CACHE_SIZE

The cool thing about this interface is that it is just a wrapper around the POSIX sysconf C function (cache arguments are non-POSIX extensions), and so it can be used from C code as well.

Tested in Ubuntu 16.04.

x86 CPUID instruction

The CPUID x86 instruction also offers cache information, and can be directly accessed by userland: https://en.wikipedia.org/wiki/CPUID

glibc seems to use that method for x86. I haven't confirmed by step debugging / instruction tracing, but the source for 2.28 sysdeps/x86/cacheinfo.c does that:

__cpuid (2, eax, ebx, ecx, edx);

TODO create a minimal C example, lazy now, asked at: https://stackoverflow.com/questions/14283171/how-to-receive-l1-l2-l3-cache-size-using-cpuid-instruction-in-x86

ARM also has an architecture-defined mechanism to find cache sizes through registers such as the Cache Size ID Register (CCSIDR), see the ARMv8 Programmers' Manual 11.6 "Cache discovery" for an overview.