What is the difference between reg and wire in a verilog module

Wire:-

Wires are used for connecting different elements. They can be treated as physical wires. They can be read or assigned. No values get stored in them. They need to be driven by either continuous assign statement or from a port of a module.

Reg:-

Contrary to their name, regs don't necessarily correspond to physical registers. They represent data storage elements in Verilog/SystemVerilog. They retain their value till next value is assigned to them (not through assign statement). They can be synthesized to FF, latch or combinatorial circuit. (They might not be synthesizable !!!)

Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. So the next question is what is this logic data type and how it is different from our good old wire/reg.

Logic:-

As we have seen, reg data type is bit mis-leading in Verilog. System Verilog's logic data type addition is to remove the above confusion. The idea behind is having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable. Logic data type doesn't permit multiple drivers. It has a last assignment wins behavior in case of multiple assignments (which implies it has no hardware equivalence). Reg/Wire data types give X if multiple drivers try to drive them with different values. Logic data type simply assigns the last assignment value. The next difference between reg/wire and logic is that logic can be both driven by assign block, output of a port and inside a procedural block like this

  logic a;
    assign a = b ^ c;                   // wire style 
    always (c or d) a = c + d;          // reg style
    MyModule module(.out(a), .in(xyz)); // wire style

Procedural blocks refers to always, always_ff, always_comb, always_latch, initial etc. blocks. While procedural assignment statements refers to assigning values to reg, integer etc., but not wires(nets).

wire elements must be continuously driven by something, and cannot store a value. Henceforth, they are assigned values using continuous assignment statements.

reg can be used to create registers in procedural blocks. Thus, it can store some value.

reg elements can be used as output within an actual module declaration. But,reg elements cannot be connected to the output port of a module instantiation.

Thus, a reg can drive a wire as RHS of an assign statement. On the other way round, a wire can drive a reg in as RHS of a procedural block.

For clear idea about declaration of reg or wire, refer the image below:

So, whenever inferring to sequential logic, which stores/holds some value, declare that variable/port as reg. Here, Q is a reg inside a module, but while instantiating this module inside some other module, then this port must be connected to a wire.

Remember, wire can only infer to combinational logic, while reg can infer to either combinational or sequential logic.

Dave's blog is a good source for detailed information. For further information, refer to synthesizing difference and Verilog wire-reg links.

Simple difference between reg and wire is, the reg is used in combinational or sequential circuit in verilog and wire is used in combinational circuit

reg is used to store a value but wire is continuely driven some thing and wire is connected to outport when module initialization but reg is con not connected