What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?

Schematic design is only useful when you're only tying together a few off-the-shelf modules (counters, adders, memory, etc). But implementing an actual algorithm (say, a cryptography hashing algorithm) is nearly impossible to do without an HDL (like VHDL or Verilog), since there's no way to describe a system at a behavioral level with schematic symbols.

Most projects are done in behavioral-style HDL because they're too complex to be synthesized by hand and drawn using logic primitives schematically.

CPLDs are generally used for glue logic and less used for processing, and generally logic is easy to implement schematically, so I think you're right when you suggest that FPGA-based designs benefit more from using an HDL.

A couple of practical aspects in addition to Jay's excellent answer:

• Bugs. The schematic tools tend to be buggier* than the rest of the toolset. This is possibly due to the preference of Verilog/VHDL over schematics in the industry, and thus schematic entry is given less attention by the software developers.
• Speed. The schematic needs to be first converted to a HDL before passing it to the synthesis tool. This can have a negative impact on build times. The generated HDL also might not be very readable if in case you need to inspect it for some reason.
• Portability. Depending on the amount of vendor specific primitives used Verilog and VHDL are more or less portable between devices. Porting schematics you either have to redraw everything or rely on the provided import/export capabilities (if any).

_{*My favourite bug in Xilinx ISE was the inability to select vertical wires.}

There are many advantages of a HDL (Hardware Description Languages) as a Design Entry standard.

The description of the functionality can be at a higher level, HDL based designs can be synthesised into a gate-level description of a chosen technology, A HDL design is more easily understood than a gate- level net-list or a schematic description and HDLs reduce errors because of strong type checking.

The hardware description languages VHDL and Verilog were designed for modelling hardware with the intention of modelling at a higher abstraction level which includes features like, concurrency, timing, hierarchy, reuse of components, state behaviour, synchronous behaviour, asynchronous behaviour, synchronization and inherent parallelism.

Issues arise during synthesis, mapping the design description to a specific process and gate implementation. This requires that you cannot use the high-level features of HDL - you must produce "synthesizable Verilog/VHDL"

So you have HDL for synthesis and HDL for Simulation and the subset that is synthesizable is tool specific.

You cannot go from a Behavioural design description to a net-list/ layout. But you can structure your design to have behavioural components that also have a synthesizable aspect that can be compared against each other. You start with the behavioural and then once that is working you rewrite for synthesis (which is a subset). You go from the general to the specific and build test-benches along the way.