why mosfet is getting very hot?

It's getting very hot because your PWM frequency is way, way to high, and you have a low-pass capacitor on the gate, for some reason.

Basically, for PWM to work properly, the FET needs to be entirely on, or entirely off the great majority of the time.

With the circuit you have, your PWM signal is being converted to an analog voltage by R3, R4, and C2. This is then partially biasing the gate on, which basically turns the FET into a voltage-controlled resistor. The resistance of the FET is then causing it to dissipate a lot of power.

You need to drop your PWM frequency massively (is it really 244 Khz?). Generally, the 500-15000 Hz ranges work well, though it can cause the motor to emit audible noise due to magnetostriction.

Then, you need to entirely get rid of C2 and significantly reduce the value of R3.

Basically, you want the waveform on the gate of the FET to be either 15V (the zener voltage of D2) or 0V 99+% of the time. Remember, the FET will only dissipate significant energy when the gate voltage is between ~2-4V (the gate threshold voltage) and ~10V (at which point the FET is entirely biased on.

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The maximum reasonable PWM frequency can be calculated using the turn-on and turn-off resistances (R2, R3) and the FET gate capacitance (which for the IRFZ44 is roughly 1470 pF). This resistance and capacitance form a RC filter which dictates the minimum switching time of the circuit.

From that, you can calculate the time spent between \$V_{g_{th}}\$ (the "FET begins to turn on", or "threshold" voltage), and the \$V_{g_{sat}}\$ (the gate saturation voltage, which is when the FET is completely on). You then take this time, and use a PWM period where the ratio of the switching time to the entire PWM cycle is very large (e.g. \$\frac{T_{switch}}{T_{pwmCycle}} < 0.01-0.05\$)

While I was writing this answer, @Connor posted an answer covering most of it. In any case...

There are a few things that need to be addressed in the presented circuit.

1. Eliminate C2 entirely: The MOSFET is being used in a switching topology, not for linear amplification, C2 completely subverts the sharp switching desired for minimal power loss. The IRFZ44N needs to be switched as rapidly as possible between fully conducting and fully blocking states, for least power wastage i.e. heat.
2. The maximum current available to charge the gate at the high-going edge of the gate input (from PWM signal) is limited by R3 = 4.7k ==> Ig < 5.1 mA. This current charges up the substantial gate capacitance at each rising edge for V_gs to rise, and is way too low. This will cause R_ds to rise very slowly, and while in this rising part of the graph, the MOSFET will waste a lot of power as heat.
   • Reduce R3 as far as the optocoupler's collector current rating will allow, or better yet:
   • Use the optocoupler to drive a BJT or smaller FET with very low gate capacitance as a switch to allow far higher gate charging current to the power MOSFET.
3. Apply the same rationale to the discharging of the gate capacitance on each falling edge of gate input. For the very high PWM frequencies indicated, a push-pull gate driver, either an integrated device or made of discrete components, is typically used instead of a passive gate drive such as shown.
4. If the rather high PWM frequency mentioned is not really needed, consider moving to a far lower PWM frequency: 500+ Hertz is often good enough, but 20-30 KHz is typical, so as to be beyond human hearing and therefore PWM noise from the motor. The higher the frequency, the greater the percentage of time the power MOSFET will be in its intermediate transition stage, rather than on or off. Therefore, more heat.
   Edit: 244 Hz as updated by OP is much more realistic.
5. The higher temperature at low duty cycles is again due to capacitor C2: It is being unable to charge up to the gate's switching voltage during the too-brief high pulses of the PWM signal. The V_gs to aim for is not the V_gs(th) of 2 to 4 Volts, but 6+ Volts, where the curve begins to flatten out in Figure 3 of the datasheet. With higher duty cycles, the capacitor does manage to breach the desired V_gs most of the time.

I agree that \$C_2\$ is probably the main source of your problem, but I would like to point out another problem.

The reason you do not observe heating for high duty cycles could be related to the fact that the opto-coupler, 4N25, has no connection to the base of the output transistor. While I am aware that many app notes for this device show no connection, I have observed (in 4N35 devices) that humidity can cause a partial conduction when the opto-coupler should be OFF (observed on a very similar circuit).

This problem seems to be worse with devices manufactured within recent years, but occurs to some degree with all of the devices I have observed (very old and very new, different manufacturers).

The problem can be observed by turning off the input to the opto-coupler and connecting an oscilloscope or voltmeter to pin 4 (reference connection to your GND_24V). If you "huff" your breath (warm moist) onto the 4N25 (specifically across pins 5 and 6), you will probably observe a voltage rise on pin 4; which will result in a partial turn-on of your MOSFET.

There are several solutions:

1. Attach a resistor from the base (pin 6) to the emitter (pin 4) of the 4N35 (typically 56K).
2. Replace the 4N25 with a similar opto-coupler that does not bring-out the base connection. The Vishay TCDT1120 is a consideration, although not the same current transfer ratio as the 4N25.
3. As a quick solution, cut off pin 6 of the opto-coupler flush with the IC package, and apply a drop of some type of moisture sealer.