Instantiate Modules in Generate For Loop in Verilog

You can apply label identifier to begin-end block with a colon after the begin (example: begin : label - end. This has always been an optional feature for generate blocks, though it is highly recommended. Quartus should not be giving an error.

It is an easy fix to satisfy Quartus-- add a label of any name you want:

genvar i;
generate
    for (i=1; i<=10; i=i+1) begin : generate_block_identifier // <-- example block name
    status whatever_status (
        .clk(clk),
        .reset_n(reset_n),
        .a(a[i]),
        .b(b[i]),
        .out(out[i])
    );
end 
endgenerate

Give your block a name:

for (i=1; i<=10; i=i+1) begin: my_status

I know this doesn't directly answer the question, but you can also declare several modules in this formation without using a generate block like so for 10 instances:

status whatever_status[9:0] (
  .clk(clk),
  .reset_n(reset_n),
  .a(a),
  .b(b),
  .out(out)
);

This is equivalent to the generate block above assuming that a, b, and out being passed are declared as [9:0]. This syntax will work as long as they're integer multiples of how they're declared in the module; they'll be spread evenly among each instance, otherwise synthesis will throw an error.

For example if a, b, and out are declared [19:0], then every 2 bits will be passed to each instance, and it is assumed they are declared as [1:0] within the module status.