Is the NAND logic gate perfectly symmetrical?

Depends on the environment.
Maybe in your circuit above and in an FPGA they are the same but in an ASIC library you find differences between the various inputs.

There will be a very small difference in that circuit because of the differences in VGS in the N stack while the circuit is sinking current during switching. M1 will be marginally slower than M2 under some conditions.

There are however likely to be other factors, say in how the circuit is laid out, that will have an equally large effect.

Define perfect. Much of what we do in EE is about modelling. The model is never perfect and at most levels of abstraction the behaviour of this circuit would be considered to be symmetrical. If we let very small differences in a circuit that typically would include tens of these gates effect us we will never get anything done.

As the M1 and M2 devices are in a different configuration, there will be a difference between the A and B inputs.

However, you may have to look very hard and carefully to see the timing or threshold effects of that difference.

When you design a logic gate into a system, you work on the maximum specifications, but expect it to behave nearer to typical. There's often a 2:1 or even 3:1 variation between max and typical specs. It's likely that any difference in performance between the A and B inputs will be much much smaller than the difference between the max and typical timings.