JTAG Clock line Termination

There are 2 reasons for using an RC end termination topology. (can only be used on signals with 50% duty cycle such as - clocks)

1. Reduce power consumption
2. Centering the eye diagram.

If you do not care about either of these then a single far end resistor will do. (screw the cap) and you can end the resistor to either Vcc or Gnd.

If you do care, then connecting the capacitor to either Gnd or Vcc should be fine. The capacitor will appear to be a short circuit during the edges, which is what you want and the average voltage between the capacitor and the resistor would be 1/2Vcc, which reduces your power.

It can reduce the impedance of the transmission line. In AC signals, the conductor behaves as transmission line. The impedance of a line in AC mode is \$j\omega L\$. It will increase as much as the frequency increase plus a \$2\pi\$ factor. We can decrease this impedance effect by adding an AC resistor in parallel to the line, i.e. by adding an RC series whose impedance is \$R+1/(j\omega C)\$. Then we have the following circuit:

^{simulate this circuit – Schematic created using CircuitLab}