List of Xilinx file suffixes (for ISE)
Quick answer: No such list exists, anywhere.
Long answer: I could tell you, but then I'd be wrong. I've been using Xilinx tools for the past 15+ years and every time they come out with a new version (or even a new service pack) things change. Sometimes even just changing various XST/MAP/PAR options will cause new files to be generated. So even if I did give you a list it would likely be out of date or just wrong.
I've created my own makefiles for building my FPGA's (I'm not using ISE's GUI environment), and it's fairly well documented what the input files to the various tools are (XST, MAP, etc). Everything else is not required and thus doesn't need to be checked into the source control system. My makefiles have a "make clean" option that removes all of the extra files. So when Xilinx releases a new version I simply recompile and the "make clean". Any file that remains (and isn't obviously something I need) is considered to be junk, and I add those files to the "make clean" list of things to delete.
Here's the start of a community wiki for the suffixes. I agree with @David Kessner. Xilinx also has this list from the command-line tools document and published a list here and here (for earliers version of their software).
File Suffix,Input or output,description
asy,output,symbol file
awc,,
bat,input,batch file. Some are generated by PlanAhead
bgn,,bitgen report file
bin,,
bit,output,FPGA bitstream
blc,output,NGCBuild report file
bld,output,build report from NGDBuild
bmm,,blockram files
bsb,,
cdc,input,ChipScope file
cel,,
cfi,input and output,provides info to Support for Platform Flash PROM Design Revisioning
cgc,,ChipScope file
cgp,,Coregen project file
cmd,,
cmd_log,output,log file
cpj,,
css,output,HTML file
csv,output,pin list
ctj,,trigger file for ChipScope
dat,,
data,,
dbg
do,input,simulation script
drc,output,design rule check
edf,output,EDIF netlist
edif,,see edf
edn,,an EDIF file suffix
f,,used for functional simulation
filter,,used in ISE to filter messages
gise,output,"contain generated data, such as process status" per http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_understanding_ise_project.htm
hdx,,used in PlanAhead for partitions
html,,report file
ipf,input,impact (programmer) project
isc,output,Configuration data in IEEE 1532 format.
jobs,,
js,output,JavaScript for some HTML report
lfp,,
ll,output, Readback information; created by bitgen
log,output,log file
lso,input,library search order input to XST.
lst,,
make,outout,from EDK tools
map,output,report file
mcs,output,prom file
mhs,,(EDK) Defines system
mrp,output,report file from map
mhs,,(EDK)
mif,input,memory initalization
mpd,,MicroProcessor Definition (EDK)
msd,output,Mask information from bitgen; used for verification
msk,output,mask information from bitgen; related to .bit
ncd,output,Native Circuit Description; after map process; used as bitgen input
ncf,,constraints for a core
new,,
ngc,output,used by NGDbuild
ngc_xst,output,
ngd,output,
ngo,output,intermediate netlist from NGDBuild
ngr,output,RTL schematic generated from XST
nky,,encryption key file, used by bitgen
nlf,output,ASCII NetGen NetGen log file that contains information on the NetGen run
nmc,,physical macros; used by NGDBuild
opt,,EDK generation options
pad,output,list of I/O pads/pins
par,output,Place and route log
pcf,,physical constraints file; used by bitgen
pdf,output,Acrobat document for core
ppr,,PlanAhead project file
prj,input,project file
prm,,PROM file generation control file
prn,output,exported ChipScope .csv file. Often lacks that suffix.
psg,output,PlanAhead strategy file
ptxw,,twx file which project navigator uses for parsing
pwr,,
pxml,,associated with partitions
rba,output,read back file created by bitgen; binary
rbb,output,read back file created by bitgen; ascii
rbd,output,read back file created by bitgen; data only
rbt,output,bit file in different format
restore,,
rtf,output,Documentation
runs,,directory in PlanAhead
rst,,
scr,,XST synthesis script
sdbl,,
sdbx,,Installation files
sdc,input,timing file [thanks @trondd]
sedif
sh,input,Linux shell script. Some are generated by PlanAhead
srcs,,directory in PlanAhead
srp,output,Synthesis log file
stx,,
sym,output,Core symbol file
tsi,,
txt,output,log file
twr,output,timing report
twx,output,
ucf,input,constraints file
unroutes,output,report file
urf,input,User Rules File; used by NGDBuild
ut,,
v,input or output,Verilog file for code. Output of coregen
vdbl,,
vbdx,,
veo,output,Verilog timing simulation file
vhd,input or output,input source VHDL file; output from Coregen
vho,output,VHDL timing simulation.
wcfg,input,ISim waveform configuration file
xaw,output,generated by Coregen
xbcd,,
xco,,use by Coregen to regenerate cores. Contains core's parameters
xdc,,
xdl,,
xise,,created by coregen
xlsx,,some report
xml,,some are output reports
xmp,,(EDK)
xmsgs,output,log file
xpa,,
xpe,,
xpi,,
xreport,output,report file
xrpt,output,report file, others are inputs to PlanAhead
xsf,,symbol file for Mentor
xst,output,associated with HTML file?
xsl,,
xst,,
unroutes,output,report file
wbd,output,Waveform Database
wxbt,,
y,,
I've created a project on Github called X-MimeTypes which aims to provide a basis which the community can use to once and for all create a proper knowledge base about the file types used in the EDA industry.
This approach has some advantages over just listing all known files in a list as done in the previous answer:
- Its on Github, thus its open and its version controlled so that you can view a full history.
The format used matches that of the OpenDesktop mimetype database. Again, there are many advantages in using this approach.
- It is proven.
- It can be extended. The current extensions allows each type to be marked as generated or not. Very useful for version control and cleanup operations etc.
- On Linux you can add this file to your system's mime database and all programs will recognize the types in the file.
- It supports the ability to classify files using magic headers etc. An example of why this is necessary is a Xilinx binary configuration file which ends with *.bin. The standard mime type database defines a .bin file as application/octet-stream, thus it will be handled as a normal binary file and it won't be picked up as a Xilinx binary configuration file. The mimetype specification easily solves this problem using magic headers. Thus, a possible correct mimetype definition for a Xilinx .bin file is:
<mime-type type="application/vnd.xilinx.bitgen.binary_configuration_file"> <comment xml:lang="en">Xilinx Binary Configuration File</comment> <glob pattern="*.bin"/> <magic priority="60"> <match type="string" value="\xff\xff\xff\xff" offset="0"/> </magic> <x:generated>true</x:generated> </mime-type>
- Anyone can file bugs against the repository, clone it etc.
- Its not vendor specific.
The EDA mime types can be accessed here.
Such a project really requires the power of the crowd, thus each small contribution will make the database more useful to many FPGA designers out there.