Memory capability and powers of 2
Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).