packed vs unpacked vectors in system verilog

bit[3:0] a -> packed array The packed array can be used as a full array (a='d1) or just part of an array (a[0]='b1)

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration. Packed arrays have an object name comes before size declaration. For example:

bit [3][7] a;

Unpacked array have an object name comes after size declaration. For example:

bit a[3];

Packed array make memory whereas Unpacked dont. You can access/declare unpacked array like this also

reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1};

You can mix both packed and unpacked array to make a multidimensional memory. For example:

bit [3:0][7:0]a[2:0].

It makes an array of 4 (i.e. 4*8) bytes with depth of 3.

Packed array are mainly used for effective memory usage when we are writing a [3:0][7:0]A[4:0] which means in 32 bit memory locations 4slices each of 8 bit are packed to form a 32 bit. The right side value means there are 5 such slices are there.

This article gives more details about this issue: http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.