Passing Generics to Record Port Types

Can you use type generics with Quartus?

Then you leave the type completely unspecified, so that you can create a FIFO of integers or any other data type:

package fifo_pkg is
  generic (type element_type);

  type fifo_in_type is record
    data_in : element_type;
    rd      : std_logic;
    wr      : std_logic;
  end record;

  type fifo_out_type is record
    data_out : element_type;
    empty    : std_logic;
    full     : std_logic;
  end record;

  component fifo is
    generic
      (
        MIN_DEPTH  : integer;
        DATA_WIDTH : integer
        );
    port
      (
        clk   : in  std_logic;
        res_n : in  std_logic;
        i     : in  fifo_in_type;
        o     : out fifo_out_type
        );
  end component fifo;

end fifo_pkg;

Then when you want to use it:

package wide_fifo_pkg is new fifo_pkg
   generic map (type => std_logic_vector(31 downto 0));

and then you can use fifo_in_type and fifo_out_type:

signal i : fifo_in_type;

If you have more than one FIFO in a design unit you can create several versions of the package and use the package prefix to get the right type:

package narrow_fifo_pkg is new fifo_pkg
   generic map (type => std_logic_vector(3 downto 0));

signal i32 : wide_fifo_pkg.fifo_in_type;
signal i4  : narrow_fifo_pkg.fifo_in_type;

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Another VHDL 2008 option: you can have an unconstrained record type:

 type fifo_in_type is record
    data_in : std_logic_vector;
    rd      : std_logic;
    wr      : std_logic;
  end record;

which you can then create subtypes of for your various uses:

subtype fifo1_data_type is fifo_in_type(data_in(31 downto 0));
subtype fifo2_data_type is fifo_in_type(data_in(15 downto 0));

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No idea if Quartus supports either of those options - please let us know!