Printing signed integer value stored in a variable of type reg

Ran into this problem as well and looked through the SystemVerilog 2012 standard, but didn't see any mention of signedness in the section about format specifiers. Here's an alternative (basically equivalent) solution that also works:

$display("acc : %d", $signed(acc))

The "$signed" function converts the input value into a signed type with the same bitwidth.

If you declare the reg as signed, $display will show the minus sign:

module tb;

reg signed [7:0] acc;

initial begin
    acc = 8'hf0;
    $display("acc : %d", acc);
end

endmodule

Prints out:

acc :         -16