Setting FPGA pins as virtual

Altera supports virtual IO and in order to get it to work, you must assigned them the property VIRTUAL_IO on (as you have done), but if these pins are connected to any signals in your design, it will no longer work.

Check out this web site that describes the steps needed to get this to work:

Declaring Virtual Pins in Quartus

Altera has a nice example on their website with a script that will make all pins virtual. I use this a lot in complex system with lots of modules for sub-system timing estimation.

  load_package flow

  proc make_all_pins_virtual {} {

     execute_module -tool map

     set name_ids [get_names -filter * -node_type pin]

     foreach_in_collection name_id $name_ids {
        set pin_name [get_name_info -info full_path $name_id]
        post_message "Making VIRTUAL_PIN assignment to $pin_name"
        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
     }
     export_assignments
  }

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/tcl/all_virtual_pins.html

The way I've done this in the past is make a wrapper with a single in pin and a single out pin, along with clock and reset pins.

Then wire a big shift register up to the in pin, and wire the real inputs of your module to the bits of that shift register. Do similar with your outputs and an out shift register.

That way you only need 4 pins - the functionality of your design will not be correct, but you can get timing information.