SPI chip select optimisation

If you really only have two devices, this can work if you're careful. Some points to consider:

1. Make sure to switch the slave select line only between full sequences and with some dead time before and after you try to transfer data.

2. Many chips use the leading edge of SS to reset their logic to the start of a new sequence. Even if you are using the same chip several sequences in a row, you will have to de-assert its SS between sequences. This means the other chip will see its SS asserted for short blips. That should be OK, but again, make sure this is only happening when the data and clock lines are quiescent.

3. The low level firmware may need to do a extra SS pulse to guarantee that the target device sees the leading edge of SS, not just SS asserted at the start of a sequence.

It should do the trick in most cases. But I think it's a bad idea to switch between slaves while the interface is active, so you should treat this issue in the master's software : let's assume slave 1 is selected. You should first stop communicating with it, then switch to slave 2, then start communicating.

In addition to points already noted, do check that all the chip-select timings on both devices will always be met. It's easy to remember to check chip-select timings for the chip you're selecting, but forget the timings for the chip you're unselecting. Many SPI chips need a minimum time between the last clock edge and chip-select disabled.