New posts in Vhdl

What does the FPGA do with unreferenced I/O pins?

VHDL that can damage FPGA

Is there a "standard" way to verify HDL of a state machine?

Altera FPGA I/O weak pull ups

VHDL - assigning array signal in a loop generates side effects

Meaning of strong and weak drive in VHDL?

What is the use of 'event in vhdl?

Do open source libraries exist for VHDL the way they do for C++ or python?

SystemC vs other HDLs

What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?