Use of tristates vs multiplexers in a RAM

It's an issue of "fan-out" or "fan-in". So your theory is more or less accurate. However there is the additional benefit of using tristate outputs that you can attach them to a bus! If you use a CMOS Multiplexer you cannot share the wires that the output is on, if you use Tri-State devices then you can share the bus with other bussed devices (under the control of an arbiter for example)... in the context of RAM, think "memory bus."

If one builds a rectangular memory array which is read using a tri-state driver in each memory cell, then one decoder circuit can control all of the cells in a row. One will need circuitry around the perimeter of the array to control it, but the amount of control circuitry will be proportional to sqrt(N)*lg(N). By contrast, if one tried to feed all the memory cells into a multiplexer, one would end up needing a lot more circuitry.

The multiplexer-based approach does have some advantages. If one built a one mega-word memory using two-way multiplexers, each bit would have to pass through 20 multiplexers, but one could achieve a very high-bandwidth pipelined memory system if each multiplexer included a latch. It would take 20 cycles to perform any particular read operation, but in 100 cycles one could begin 100 different reads. Since the signal wouldn't have to go very far in each cycle and wouldn't be driving any large buses, the cycle rate could be extremely high.

The issue of whether to use multiplexers or buses ends up being somewhat similar to the question of whether to use data repeaters when sending information over long distances. On the one hand, data repeaters add delay. On the other hand, the time required for a signal transition at one end of a stretch of copper to cause a transition at the other end is asymptotically proportional to the square of the length (since adding length adds both resistance and capacitance). Adding a repeater in the middle of a long wire may end up improving speed since the long run will be replaced by two shorter ones with somewhere between a quarter and half of the longer delay.

If one were to double the width and length of a memory array without improving the 'oomph' of the row and column driver circuits, one would more than double the time required to switch the rows and columns. By contrast, if one were to use four smaller memory arrays and multiplex the outputs, one would only add a constant to the access time. Faster memories are subdivided into more small arrays connected by multiplexers; cheaper memories use fewer multiplexers but aren't as fast.