Verilog Netlist format with "\"

The verilog escaping mechanism is to put \ at the start of an identifier and a " " at the end. The trailing space is mandatory. Within those, anything is a legal verilog name. It's pretty ugly.

It looks like the compiler has "flattened" part of the design, what might have been inv.qmul.p has become one identifier and the module hierarchy has gone.

The \ is an escape character, which escapes the entire string of ascii characters until the next space character (note the space before the closing parenthesis of .B).

So \in_a[9], is literally just a net named in_a[9]. It's no longer part of any bus, it's just a net name that happens to have some brackets in it. Similar for inv/qmul/p, this is just a net name with some slashes in it (I've seen synthesizers generate nets like this when it wants to preserve a net's original hierarchy for some reason, though I couldn't say exactly why).

I think that you could have a verilog net named wire \@#$%{{[[@#$^@ ; and it wouldn't complain, but of course I've never tried :)