VHDL recursive component/entity

You can use recursion in VHDL. But you need to encapsulate your instantiation in an if-generate statement. Something like:

recursive_structure : if size/2 > 0 generate 
    smallerEntity : entity <library_name>.myEntity(structural)
        generic map (
            size => size/2
        )
        port map ( 
            ... 
        );
end generate recursive_structure;