VHDL vs. Verilog
I can't tell you which to learn, but here's some contrasting points (from a very VHDL-centric user, but I've tried to be as fair as possible!), which may help you make a choice based on your own preferences in terms of development style:
And keep in mind the famous quote which goes along the lines of "I prefer whichever of the two I'm not currently using" (sorry, I can't recall who actually wrote this - possibly Janick Bergeron?)
VHDL
- strongly-typed
- more verbose
- very deterministic
- non-C-like syntax (and mindset)
Lots of compilation errors to start with, but then mostly works how you expect. This can lead to a very steep feeling learning curve (along with the unfamiliar syntax)
Verilog
- weakly-typed
- more concise
- only deterministic if you follow some rules carefully
- more C-like syntax (and mindset)
Errors are found later in simulation - the learning curve to "feeling like getting something done" is shallower, but goes on longer (if that's the right metaphor?)
Also in Verilog's favour is that high-end verification is leaning more and more to SystemVerilog which is a huge extension to Verilog. But the high-end tools can also combine VHDL synthesis code with SystemVerilog verification code.
For another approach entirely: MyHDL - you get all the power of Python as a verification language with a set of synthesis extensions from which you can generate either VHDL or Verilog.
Or Cocotb - all the power of Python as a verification language, with your synthesisable code still written in whichever HDL you decided to learn (ie VHDL or Verilog).
SystemC is also a good option for an HDL. SystemC supports both System level and Register Transfer Level (RTL) design. You need only a C++ compiler to simulate it. High-Level Synthesis tools will then convert SystemC code to Verilog or VHDL for logic synthesis.
I learned both the same week. VHDL is like ADA/Pascal and Verilog is like C. VHDL is more verbose and more painful to get a compile, but once you get a compile your chances at success are better. At least that is what I found. Verilog, like C, is quite content at letting you shoot yourself in the foot. Some industries like aerospace/govt lean toward VHDL, others lean toward Verilog. The problem I find with both is the test bench capabilities, and when trying to learn and trying to get from simulation to silicon/FPGA writing synthesizable only code is another level of education.
There is a language I really like called CDL. It is strictly synthesizable, you write your test benches in other ways, it generates synthesizable Verilog which you can take into other tools. Unfortunately the CDL docs are lacking, I hope to get some samples out in the world to show how much easier it is to use than either Verilog or VHDL, but just dont have that done. It comes with its own sim/test environment. With CDL and GTKWave you can do a considerable amount of work.
Another tool called Verilator, is fairly rigid in keeping your Verilog clean. It is a free Verilog simulator with a very easy way to attach to the sim or create test benches in C/C++. You can use Verilog as well, doesn't limit you there. There is Icarus Verilog as well, which is bigger and more well known, but I would recommend Verilator if you want to learn Verilog. For VHDL there is GHDL, my experience with it was not as good as Verilator, but at least there is a free tool for trying to get your feet wet. If you have software programming experience you are likely to pick up and enjoy Verilog faster than VHDL.
I definitely agree with Leon, try both. fpga4fun and other web pages has some good info and some of those pages will give you both the Verilog and VHDL equivalents for the topic they are discussing. I find pages like those the most useful for comparing the two languages. If using an HDL is something you want to do in your career, I recommend having at least some capabilities with both, maybe really good with one but don't be completely unable to use the other.
Many holy wars have been fought over this. One particular disadvantage of Verilog is its non-deterministic behavior. http://www.sigasi.com/content/verilogs-major-flaw