What are the sizes of tword, oword and yword operands?
I have checked it with two approaches for NASM: source code and empirical.
Source code
Source at: http://repo.or.cz/w/nasm.git
Then:
git grep -C2 tword
And we fall upon:
switch (size) {
case 1:
return "byte";
case 2:
return "word";
case 4:
return "dword";
case 8:
return "qword";
case 10:
return "tword";
case 16:
return "oword";
case 32:
return "yword";
case 64:
return "zword";
default:
return "???";
}
Empirical
git log -p
and git tag --contains
tell me that zword
was added in 2.11, and since I'm on 2.10 and lazy, I'll omit that one.
On our .asm
file:
section .bss
resb1 resb 1
resw1 resw 1
resq1 resq 1
rest1 rest 1
reso1 reso 1
resy1 resy 1
; Just to read the objdump better.
resb2 resb 1
Then compile and:
objdump -D -j .bss main.o
gives:
00000000 <resb1>:
...
00000001 <resw1>:
...
00000003 <resd1>:
3: 00 00 add %al,(%eax)
...
00000007 <resq1>:
...
0000000f <rest1>:
...
00000019 <reso1>:
...
00000029 <resy1>:
...
00000049 <resb2>:
...
If we take the differences between each position, we reach the same conclusion as before.
zword menemonic
For the ZMM
registers added by AVX-512: https://en.wikipedia.org/wiki/AVX-512
I wonder what Intel will do when the letters of the alphabet end.
Looking at the nasm source, it looks like:
- 'oword'/'DO' is 8 times as big as "word" (O for "octoword"), synonymous with dqword ("double-quad"); that would be 128 bits, corresponding to the size of an SSE vector register.
- 'tword'/'DT' is 80 bits (T for "ten bytes"), the full size of an Intel x87 floating point register.
- 'yword'/'DY' is 256 bits, and the Y is presumably mnemonic for the YMM names of the 256-bit vector registers in the Intel AVX extensions.
- 'zword'/'DZ' is 512 bits, Z for the ZMM names of the 512-bit vector registers in the Intel AVX-512 extensions.
So, it's not exactly a logical naming convention; "it just growed".