What is meant by the FENCE instruction in the RISC-V instruction set?

The RISC-V ISA uses a relaxed memory model where the order of loads and stores performed by one thread may be different when seen by another. This is done to enable techniques to increase memory system performance.

For example, Thread 1 may execute:

• Load A
• Store B
• Store C

But Thread 2 could see the loads and the stores out of order with regard to the first thread:

• Store C
• Load A
• Store B

The FENCE ensures that all operations before the fence are observed before any operation after the fence. So if the above changed to:

Thread 1:

• Load A
• Store B
• FENCE
• Store C

Then Thread 2 would be guaranteed to see the load to A and the store to B before the store to C, but still could see the store to B before the load of A.

Thread 2:

• Store B
• Load A
• Store C

Source: RISC-V ISA (Section 2.7 page 20)

Incorporating Chris P's comment:

I/O (I and O flag) and memory accesses (R and W) can be controlled separately with the FENCE instruction For example: You can control that only memory writes should be ordered by FENCE but memory reads and I/O operations are unaffected by FENCE. For this, the PW and SW bits should be set. If only PW (predecessor write) is set, then FENCE will ensure, that all memory writes before FENCE are also observed by other harts (threads) before FENCE, but memory writes after FENCE can also be observed before.