What is the point of having a level-based interrupts?

Level-based interrupts can safely be shared and cascaded easily and reliably; by contrast, reliably sharing edge-triggered interrupts is often difficult and sometimes impossible.

When using level-based interrupts, an interrupt handler can simply ask each possible interrupt source in turn "Do you need attention", and service it if so. Once it's done, the handler can return. If an interrupt source which was polled early in the sequence decides it needs attention while a later source is being serviced, the processor will notice that the IRQ pin is still active and re-trigger the interrupt handler, thus allowing the late-arriving interrupt to be serviced.

When using non-cascaded edge-triggered interrupts, things get more complicated. After an interrupt handler has gone through and serviced everyone, it must then go through and re-poll everyone to find out if a previously-polled device has decided that it needs service. Only after every device has consecutively reported that it does not need service would it be safe for the interrupt to return. Note that if devices that want service keep their "need service" indication active, returning from an interrupt handler at a time when a device needs service may render that interrupt permanently useless.

It may be useful for an I/O pin to have some edge-capture logic which, when an edge arrives, sets a latch and outputs a "need-service" indication until software clears it. Such a thing might appear on the very front end as an edge-sensitive interrupt. At any downstream point, however, it's better to have interrupt logic demand that an interrupt be serviced at all times when any upstream point is not satisfied.

One obvious situation where level based interrupts are useful is for the situation where the signal is already in that state when the code begins to monitor the signal.

Let's consider a typical example ...

Signal: "Case_Over_Temperature" Goes low when the ambient in the box is too high for normal operation..

Obviously, this signal could go low at any time, either because we are making too much heat, or because the box is installed in a hot location.

Obviously, on power up that line could be in either condition. Let's assume for the moment that the power-on code doesn't just go look but relies on the interrupt instead. If the interrupt is edge triggered and the signal is already low, when the interrupt gets enabled the appropriate code will not be executed. Level sensitive interrupts would be prudent here.

Similarly, if the processor is put to sleep and is not set to wake on that interrupt, that line can go low at any time. When whatever else wakes it up happens, you want the interrupt to fire at that time.

Indeed, arguably, with the prevalence of sleep mode processors, level based interrupts have become more useful.

However, as with all things code related, there is always more than one way to "skin a cat". If you don't use level based, the wakeup code needs to go poll the interrupt pins if they are not automatically queued by the processor.

Obviously, level triggered also comes with it's own set of issues in that the code has to handle knowing that it has already handled the condition etc.

It's somewhat the other way around: why have awkward edge-triggered interrupts when you can have the easier level-triggered?

Edge triggered interrupts are more susceptible to noise spikes and harder to filter. They're then riskier to run off-board or up cables. The interrupt can't be withdrawn by the source.

Level-triggered interrupts stay on until the CPU acknowledges the source. So there's the solid base of full handshaking. The CPU can filter noise out of the interrupt signal in almost any way it wants, it's just increasing the interrupt response time. If the application requires and allows for well-filtered signals, level triggering is adaptable.

I first saw edge-triggered interrupts used for NMIs on CPUs like the Z80 and 6502, while maskable interrupts used level triggered. The NMIs used edge-triggered simply to stop a stuck pin or stuck driving circuit from keeping the CPU re-entering the NMI ISR forever. The NMI must show activity to get another one.

The answer, of course, is that they both have their applications. But level-triggered is the starting point and edge-triggered gone to because there's a special case.