What is the purpose of the `std_logic` enumerated type in VHDL?

• 'X' usually is caused by two statements driving the same signal in opposite directions,i.e., '0' and '1'
• 'Z' is used to build a tri stated output/input
• 'L' and 'H' are used to model a pulldown or pullup respectively
• '-' is used in comparisons when you don't care about certain bits in a vector

std_logic is basically a single wire or bit. You can use logical operators (and, or, xor, etc.) on them. When simulating a design I believe I have only seen 'X', '0', or '1'. Obviously you want '0' or '1'. An 'X' indicates that the value is unknown (possibly not connected to anything or there is a glitch in the signal). Also, std_logic_vector can be used for signals that need to be more than 1 bit wide. I'm not sure if this answers your question...

The std_logic type was introduced by the IEEE-1164 standard as an accurate representative of a single wire or bit. The VHDL language itself does not provide a single-bit type that is robust enough to represent "real" logic. That is, to represent all the possible states of modelable and synthesizable logic in a modern programmable logic device.

Early in the history of VHDL, different developers were essentially authoring their own versions of std_logic out of the need to represent real-world signals. IEEE-1164 introduced this standardized logic type in an effort to enhance interoperability of code written by different developers for different architectures.

The wikipedia article for the standard provides a succinct description:

http://en.wikipedia.org/wiki/IEEE_1164