Why is length matching performed with the clock trace length as the target length?

Data is sent in respect to the clock signal.

Data has to be stable before the clock edge (setup time) and it has to be stable after the clock edge (hold time).

If the clock wiring is too long compared to data, clock will appear too late to be within hold time specs, and if data wiring is too long compared to clock, clock will appear too early to be within setup time specs.

Every single signal is observed in relation to the clock; i.e. what matters for the receiver to "sample" all the parallel signals at exactly the right point in time, +- the allowable skew.

Example: Say, we have a bus where the allowable skew is +-50 ps, so that the receiver still gets the signals close to their maximum when it samples at the rising clock edge.

Now, it doesn't really help if all the signals have +-50 ps to each other, or say, to the first data signal – if data[19] has +40 ps delay to data[0], and data[0] has +20 ps delay to the clock, then data[19] has +60 ps delay to the clock and simply won't be sampled at the right time.