Will multiple chips outputing onto a bus for a few nanoseconds cause damage?

Typically the situation was avoided by the outputs being open-collector instead of tristate, with a pullup resistor to +5V completing the circuit. If one device drove the shared line low and the other went open-collector, the shared line would stay low. If there was only a conflict for a very short time, this would cause no problems at all.

For a practical example of this, the CAN bus is widely used in industry (particularly in cars) and operates in exactly this way. Every device's output is open-collector with a current limit, and one device (and one only) contains the pullup resistor. In an industrial/automotive context where devices can and do go wrong, and wires can also be shorted high or low, this ensures that no device's output can damage another device, however it goes wrong. In addition, the CAN bus driver for each device monitors the bus to check that it goes to the expected state, and reports bus errors to the application if it finds a conflict where someone else is stomping over its data.

In practise this is unlikely to damage the chips. However it will give instantaneous current spikes on outputs where high and low are shorted, which does unpleasant things to EMC emissions. Designers in the 70s and 80s were much less concerned about EMC, so it's likely that many circuits went out of the door with exactly this problem.

There are a number of ways to create nonoverlapping enables for bus devices. Perhaps the simplest is to add the clock signal itself to your equations. Then, only one device at a time is enabled while the clock is high, and no devices at all are enabled while it is low. (Or vice-versa if you're using the rising edge of the clock to capture data.)

Normally, the output-enable function of most devices is fast enough that "wasting" half of each cycle in this way does not cause a timing problem. But if it does, one workaround is to modify the duty cycle of the clock as needed.

If it would cause damage, how was this situation avoided in the 1970's-80's?

manual design that compensated the delay.

Whether this will cause damage depends on your technology, so no general advice can be given; however, for a transient of 10ns to have effect, your system needs to have a bandwidth > 100MHz, so that's something you can actively avoid.