Counter for 20 GHz clock

15 years ago I designed a two parameter digitizer (energy and time) to measure time of flight. For this system I used a constant current source into a cap held in reset by a JFET. On receiving the trigger (NIM fast logic, level shifting kept in the analog (as opposed to saturated switching) regime, the JFET opened, and I was able to achieve 50ps resolution by digitizing the linear ramp, and interpolating from a 62.5MSPS ADC in an FPGA . The circuit was quite simple, and matched simulations perfectly.

Some long while ago, as a thought experiment, I 'designed' a time capture FPGA.

It had a ring oscillator, conventional other than the fact it had 41 inverters. The period was thus much much lower than the delay of any gate. The FPGA process had individual gate delays down in the 10s of pS where the routing was local and the fan-out low, but could only handle system clocks in the order of 100s of MHz, due to multiplexing, routing and loading delays between blocks.

The time capture process then used 41 D-latches, each capturing the input transition, but of course clocked at different phases of the ring counter cycle. The outputs of the D-latches could be interpretted as a 'thermometer code', interpolating the input transition to sub cycle precision, with a resolution in the 10s of pS. Another 41 D-latches captured a reference clock.

There are two main difficulties with such a structure. The first is getting the synthesis tools to lay out the ring counter and lines to the D-latches in a high-speed way. This part would probably be better handled by direct manual placement. It might need a specific type of small high speed FPGA, perhaps one without multipliers and processor cores in! The second is race-free handling of the overlap between the thermometer code, and a conventional counter clocked by the lower frequency reference, but it can be done, taking care of metastability issues.

I didn't pursue it as I found a better way of solving the problem, but it was fun.

As someone already pointed out, there are dedicated ICs for that purpose.

If you want to do it on your own a possible approach would be to use so called Vernier delay lines.

You have two delay lines (chains of buffers) where one chain uses faster buffers than the other. The resolution of your measurement is equal to the difference of the delays of the elements in the fast and "slow" chain.

For measuring the delay you send the start pulse through the slow chain and the stop pulse through the fast chain. The stop pulse travels faster and finally will catch up with the start pulse. The number of buffers required will be a measure for the delay.

My focus is on IC design, so I am not sure if this could be done with an FPGA. Literature suggests that it is possible, though.