Experiences with Test Driven Development (TDD) for logic (chip) design in Verilog or VHDL

I write code for FPGAs, not ASICS... but TDD is my still my preferred approach. I like to have a full suite of tests for all the functional code I write, and I try (not always successfully) to write testcode first. Staring at waveforms always happens at some point when you're debugging, but it's not a good way of validating your code (IMHO).

Given the difficulty of performing proper tests in the real hardware (stimulating corner cases is particularly hard) and the fact that a VHDL-compile takes seconds (vs a "to hardware" compile that takes many minutes (or even hours)), I don't see how anyone can operate any other way!

I also build assertions into the RTL as I write it to catch things I know shouldn't ever happen. Apparantly this is seen as a bit "weird", as there's a perception that verification engineers write assertions and RTL designers don't. But mostly I'm my own verification engineer, so maybe that's why!

I use VUnit for test driven development with VHDL.

VUnit is a Python library that invokes the VHDL compiler and simulator and reads the results of the simulation. It also provides several nice VHDL libraries that makes it a lot easier to write better test benches, such as a communication library, logging library and a checking library.

There are many possibilities since it is invoked from Python. It is possible to both generate test data, as well as check the output data from the test in Python. I saw this example the other day where they used Octave - a Matlab copy - for plotting test results.

VUnit seems very active and I have several times been able to actually ask questions directly to the developers and gotten help quite quickly.

A downside is that it is harder to debug compilation errors since there are so many function/procedure variations with the same name in the libraries. Also, some stuff is done behind the scene by preprocessing the code, which means that some errors might show up in unexpected places.

The SystemVerilog extensions to the IEEE Verilog Standard include a variety of constructs which facilitate creating thorough test suites for verifying complex digital logic designs. SystemVerilog is one of the Hardware Verification Languages (HVL) which is used to verify ASIC chip designs via simulation (as opposed to emulation or using FPGA's).

Significant benefits over a traditional Hardware Design Language (Verilog) are:

• constrained randomization
• assertions
• automatic collection of functional and assertion coverage data

The key is to have access to simulation software which supports this recent (2005) standard. Not all simulators fully support the more advanced features.

In addition to the IEEE standard, there is an open-source SystemVerilog library of verification components available from VMM Central (http://www.vmmcentral.com). It provides a reasonable framework for creating a test environment.

SystemVerilog is not the only HVL,and VMM is not the only library. But, I would recommend both, if you have access to the appropriate tools. I have found this to be an effective methodology in finding design bugs before becoming silicon.