Can an SPI slave start a transmission in full-duplex mode?
No, with SPI, all communications are driven by the master device. You are correct that the master cannot simply provide a continuous clock; there would be no way to detect the byte boundaries.
A slave device will often have a separate output pin to signal to the master that it has data available. This pin is connected to an input on a microcontroller and is often used as an interrupt.
Then, the device can assert the pin, causing the microcontroller to spin up the SPI bus.
For more detailed information, please read on :) This is a slightly-modified version of an explanation found here:
The slave device can only communicate when it is provided a clock from the master. This complicates reading from the slave, because you have to cause the master to provide enough clock cycles for the slave to respond.
When you send an SPI command from the master, two transmissions actually happen during the same eight clock pulses. The first is that your byte is clocked out of the MOSI line. But, at the same time, data is being clocked in to the microcontroller via the MISO line.
But since the slave doesn't get the full command until the end of these transactions, it doesn't present any data to the bus. This results in a received value of 0x00 or 0xFF.
Then you need to provide an additional eight clocks to allow the slave to return the actual value. In many code implementations, this is done by sending a "dummy byte" to the slave.
Note that, in the first transmission, the master ignores whatever arrives from the slave. In the second transmission, the slave ignores whatever is sent by the master.
That describes the general case. There can be additional complexities. For example, some slave ICs will actually output some sort of status byte at the same time they are receiving a command from the master. So, in this case, the master shouldn't discard the first received byte.
No, master is the one that arbitrates the chipselects and drives the clock. A slave will always only listen to clock and chipselect. Data transfer can be full duplex still. There are some implementations where the clock can be continuous, but it does not matter much as the chipselect is used to synchronize the byte boundaries anyway. But then there are multimaster systems, so basically you can have some mechanism for the devices to decide who is slave and master. Or just include a separate "interrupt" wire for the slave to signal the master that it has a data packet for the master.