VHDL optimization

My guess is that there will be no difference. However, the results will depend greatly on the specific tool set you use as well as the target architecture (FPGA? ASIC?).

By the time the tools get to the placement and routing steps they have long forgotten what your RTL looked like. In fact, the gates themselves may have been optimized away or the logic function could be modified in such a way that there is no gate in the final design corresponding to your NOR gates...this is almost guaranteed to be the case in an FPGA.

It does not make a difference.
Synthesis tools are very, very good at optimizing.

As to "speed" versus "area": every synthesis tool I know has settings where you can choose which one you prefer. Normally the tools will optimize until it meets the timing constraints and then stop. Which means you get the smallest design which still meets timing.

The only time your gates are not "moved around" is if you explicitly tell the synthesis tool to not do that. It falls under the category where you tell the tool not to optimize across module boundaries. (e.g. 'no flattening' or 'flattening off' or a tick box with some 'keep boundaries' option.