"recommended that CLK begin toggling within 150 ms ... to ensure long-term reliability of the device" -- why?

The clock undoubtedly operates charge pumps within the chip that provide bias voltages for various functional areas. Without proper bias, leakage currents are probably higher than the transistors are really designed to handle long-term.

If tristate bus contention can occur, the shoot thru energy temperature rise would be of the same amount of time. It seems the power on reset is not enough.