SRAM isn't blank on powerup, is this normal?

Unless you have an initial state programmed, it will be more or less random. Although this may vary with different SRAM implementations. You also say "blank". Some might think that random is "blanker" than all 0's.

SRAM memory stores memory on back to back inverters.

This forms a bi-stable system (two very stable states with metastability dividing them). So, upon power up the back to back inverters are briefly metastable.

This happens because as the voltage ramps up (from being turned on), both NMOS and PMOS of the back to back inverters would be 'equally' on, holding both bitnodes at half the supply voltage (this is the metastable state). Eventually some thermal noise (or any process that introduces variation) pushes or pulls this value down or up a little bit. At this point the bitnodes snap into one of their bistable states.

• As an example, consider \$ Q=Q'=\frac{V_{supply}}{2} \$
• Next, some thermal noise on Q increases the voltage up to \$ \frac{V_{supply}}{2} + \delta \$
• Now, the NMOS feeding Q' gets turned on just a little bit more. And the PMOS feeding Q' gets turned off just a little bit more. So Q' pulls down from \$ \frac{V_{supply}}{2}\$ to \$ \frac{V_{supply}}{2} - \delta \$.
• Next, since the voltage at the gate of the FET's driving Q node decreases, the PMOS turns on a little more (and NMOS turns off more). This causes Q to increase further to the supply. And this quickly snaps Q' to 0 and Q to 1.

In fact, there is even a paper "Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers"

One very helpful plot contained in the paper is below. The dotted line represents the supply voltage ramping up:

• On the left-side, everything is equal. In this case, random variation due to temperature or another number of factors bumps the bitnode into one state or the other.
• On the right side, there is a bitnode which is skewed (purposefully or otherwise) to be much more likely to initialize in a particular state.

Depending on how each bitnode in the SRAM you are using currently was fabricated, you end up with more or less of one of the two situations above. In both cases, unless you intentionally skewed the SRAM, the initial outputs would look more or less random. In the left-hand situation, each subsequent powerup would generate more random patterns. In the right-hand situation, the initial startup would be seemingly random. But further powerups would cause the SRAM to tend to further certain states.

Having worked with SRAM for many years, I can tell you that it will power up with seemingly random contents, although I have seen devices that power up with nearly the same random looking contents each time. If the power off cycle is short enough (depending on power supply characteristics and the number & value of bypass capacitors), large fragments of previously written data can linger in the SRAM through power cycles - although the content will be corrupted.

A single bit is stored in a SRAM in a circuit of 6 or more transistors. If you want a defined power on reset behaviour for the SRAM, each RAM cell would need more than 6 transistors only. The needed chip area will be substantially larger and the SRAM chips will be more expensive. This is a parallel power on reset of all bits at the same time. A serial reset would require an oszilator, an address counter and enough time during power up to resets all RAM bits or bytes sequentially. If the processor accesses the SRAM before the serial power on reset is finished, errors may occur and data may be lost or changed.

There are programming environments for microprocessors with detailed memory mapping of several RAM areas. You may define an area with or without a power on reset as required by the application. Several different areas within the same SRAM are possible. It is not always necessary to reset the whole SRAM on programm start.