New posts in Fpga

What is a "half latch" in an FPGA?

FPGA: count up or count down?

What does the FPGA do with unreferenced I/O pins?

VHDL that can damage FPGA

Hardware sources of entropy on an FPGA

Altera FPGA I/O weak pull ups

Can a NOT gate be used to achieve 180 degree phase shift?

Do I need to reset my FPGA design after startup?

How to configure HCI UART for 3 Mbps?

Counter for 20 GHz clock