New posts in X86

Why does using MFENCE with store instruction block prefetching in L1 cache?

Count each bit-position separately over many 64-bit bitmasks, with AVX but not AVX2

Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?

Legacy BIOS bootloader to bootstrap real-mode code in second stage

Performance of "conditional call" on amd64

Problem switching to v8086 mode from 32-bit protected mode by setting EFLAGS.VM to 1

Why is linear read-shuffled write not faster than shuffled read-linear write?

How can x86 bsr/bsf have fixed latency, not data dependent? Doesn't it loop over bits like the pseudocode shows?

what is jmpl instruction in x86?

Fast way to get a close power-of-2 number (floating-point)