Using parameters to create constant in verilog

Your looking for the replication operator. The syntax is {replication_constant{value}}.

An example of creating a bus of size WIDTH to all zeros.

parameter WIDTH = 3;
wire [WIDTH-1:0] n = {WIDTH{1'b0}};

For full description of the replication operator, see IEEE std 1800-2012 § 11.4.12.1 "Replication operator"

To expand Gregs answer and answer what if you wanted 1 then all 0's.

Use a mixture of concatenation {a,b} and replication {width{c}}:

wire [WIDTH-1:0] n = { 1'b1, {WIDTH-1{1'b0}} } ;

While the '0 or '1 syntax is in use in SystemVerilog 'b0 for width matching is valid in older Verilog. In verilog-95 it would only width match upto 32 bits but that has since been rectified.

Example defining the reset values on flip-flops :

reg [7:0] a;
always @(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    a <= 'b0 ;
 ...