Verilog question mark (?) operator

That's a ternary operator. It's shorthand for an if statement

Format:

condition ? if true : if false

Example:

tone[23] ? clkdivider-1 : clkdivider/2-1

Translates to something like (not correct syntax but I think you'll get it):

if tone[23] is 1, counter = clkdivider-1
else counter = clkdivider/2-1

Here are two examples of a 2 to 1 MUX using if statement and ternary operator.

On the asic-world website, it is covered under Conditional Operators

Another way of writing, e.g. the following Verilog:

q <= tone[23] ? clkdivider-1 : clkdivider/2-1;

in VHDL would be:

q <= clkdivider-1 when tone[23] else clkdivider/2-1;

Related